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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TTBCR2, Translation Table Base Control Register 2</h1><p>The TTBCR2 characteristics are:</p><h2>Purpose</h2>
        <p>The second control register for stage 1 of the PL1&amp;0 translation regime.</p>

      
        <p>If <span class="xref">FEAT_AA32HPD</span> is not implemented then this register is not implemented and its encoding is <span class="arm-defined-word">UNDEFINED</span>. Otherwise:</p>

      
        <ul>
<li>When the value of <a href="AArch32-ttbcr.html">TTBCR</a>.{EAE, T2E} is not {1, 1} the contents of TTBCR2 are treated as zero for all purposes other than reading or writing the register.
</li><li>When the value of <a href="AArch32-ttbcr.html">TTBCR</a>.{EAE, T2E} is {1, 1} TTBCR2 is used with <a href="AArch32-ttbcr.html">TTBCR</a>.
</li></ul>
      <h2>Configuration</h2><p>AArch32 System register TTBCR2 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-tcr_el1.html">TCR_EL1[63:32]</a>.</p><p>This register is present only when EL1 is capable of using AArch32 and FEAT_AA32HPD is implemented. Otherwise, direct accesses to TTBCR2 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>TTBCR2 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="13"><a href="#fieldset_0-31_19">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18-1">HWU162</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17-1">HWU161</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16-1">HWU160</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15-1">HWU159</a></td><td class="lr" colspan="1"><a href="#fieldset_0-14_14-1">HWU062</a></td><td class="lr" colspan="1"><a href="#fieldset_0-13_13-1">HWU061</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12-1">HWU060</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11-1">HWU059</a></td><td class="lr" colspan="1"><a href="#fieldset_0-10_10">HPD1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">HPD0</a></td><td class="lr" colspan="9"><a href="#fieldset_0-8_0">RES0</a></td></tr></tbody></table><h4 id="fieldset_0-31_19">Bits [31:19]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-18_18-1">HWU162, bit [18]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr1.html">TTBR1</a>.</p>
    <table class="valuetable"><tr><th>HWU162</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD1 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-18_18-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-17_17-1">HWU161, bit [17]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr1.html">TTBR1</a>.</p>
    <table class="valuetable"><tr><th>HWU161</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD1 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_17-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-16_16-1">HWU160, bit [16]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr1.html">TTBR1</a>.</p>
    <table class="valuetable"><tr><th>HWU160</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD1 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-16_16-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15-1">HWU159, bit [15]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr1.html">TTBR1</a>.</p>
    <table class="valuetable"><tr><th>HWU159</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr1.html">TTBR1</a>, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD1 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD1 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_15-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-14_14-1">HWU062, bit [14]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[62] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr0.html">TTBR0</a>.</p>
    <table class="valuetable"><tr><th>HWU062</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD0 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-14_14-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_13-1">HWU061, bit [13]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[61] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr0.html">TTBR0</a>.</p>
    <table class="valuetable"><tr><th>HWU061</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD0 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-13_13-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12-1">HWU060, bit [12]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[60] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr0.html">TTBR0</a>.</p>
    <table class="valuetable"><tr><th>HWU060</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD0 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-12_12-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-11_11-1">HWU059, bit [11]<span class="condition"><br/>When FEAT_HPDS2 is implemented:
                        </span></h4><div class="field">
      <p>Hardware Use. Indicates <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> hardware use of bit[59] of the stage 1 translation table Block or Page entry for translations using <a href="AArch32-ttbr0.html">TTBR0</a>.</p>
    <table class="valuetable"><tr><th>HWU059</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>For translations using <a href="AArch32-ttbr0.html">TTBR0</a>, bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> purpose if the value of TTBCR2.HPD0 is 1.</p>
        </td></tr></table>
      <p>The Effective value of this field is 0 if the value of TTBCR2.HPD0 is 0 or the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_11-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_10">HPD1, bit [10]</h4><div class="field">
      <p>Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by <a href="AArch32-ttbr1.html">TTBR1</a>.</p>
    <table class="valuetable"><tr><th>HPD1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Hierarchical permissions are enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Hierarchical permissions are disabled if <a href="AArch32-ttbcr.html">TTBCR</a>.T2E == 1.</p>
        </td></tr></table><p>When disabled, the permissions are treated as if the bits are 0.</p>
<p>The Effective value of this field is 0 if the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-9_9">HPD0, bit [9]</h4><div class="field">
      <p>Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by <a href="AArch32-ttbr0.html">TTBR0</a>.</p>
    <table class="valuetable"><tr><th>HPD0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Hierarchical permissions are enabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Hierarchical permissions are disabled if <a href="AArch32-ttbcr.html">TTBCR</a>.T2E ==1.</p>
        </td></tr></table><p>When disabled, the permissions are treated is as if the bits are 0.</p>
<p>The Effective value of this field is 0 if the value of <a href="AArch32-ttbcr.html">TTBCR</a>.T2E is 0.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_0">Bits [8:0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing TTBCR2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0010</td><td>0b0000</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T2 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T2 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TRVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TRVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        R[t] = TTBCR2_NS;
    else
        R[t] = TTBCR2;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        R[t] = TTBCR2_NS;
    else
        R[t] = TTBCR2;
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' then
        R[t] = TTBCR2_S;
    else
        R[t] = TTBCR2_NS;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0010</td><td>0b0000</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T2 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T2 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        TTBCR2_NS = R[t];
    else
        TTBCR2 = R[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        TTBCR2_NS = R[t];
    else
        TTBCR2 = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' &amp;&amp; CP15SDISABLE == Signal_High then
        UNDEFINED;
    elsif SCR.NS == '0' &amp;&amp; CP15SDISABLE2 == Signal_High then
        UNDEFINED;
    else
        if SCR.NS == '0' then
            TTBCR2_S = R[t];
        else
            TTBCR2_NS = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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